Espressif Systems /ESP32-S3 /SPI0 /CACHE_FCTRL

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Interpret as CACHE_FCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CACHE_REQ_EN)CACHE_REQ_EN 0 (CACHE_USR_CMD_4BYTE)CACHE_USR_CMD_4BYTE 0 (CACHE_FLASH_USR_CMD)CACHE_FLASH_USR_CMD 0 (FDIN_DUAL)FDIN_DUAL 0 (FDOUT_DUAL)FDOUT_DUAL 0 (FADDR_DUAL)FADDR_DUAL 0 (FDIN_QUAD)FDIN_QUAD 0 (FDOUT_QUAD)FDOUT_QUAD 0 (FADDR_QUAD)FADDR_QUAD

Description

SPI0 external RAM bit mode control register.

Fields

CACHE_REQ_EN

Set this bit to enable Cache’s access and SPI0’s transfer.

CACHE_USR_CMD_4BYTE

Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

CACHE_FLASH_USR_CMD

1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.

FDIN_DUAL

When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.

FDOUT_DUAL

When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.

FADDR_DUAL

When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.

FDIN_QUAD

When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.

FDOUT_QUAD

When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.

FADDR_QUAD

When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.

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