SPI0 external RAM bit mode control register.
| CACHE_REQ_EN | Set this bit to enable Cache’s access and SPI0’s transfer. |
| CACHE_USR_CMD_4BYTE | Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. |
| CACHE_FLASH_USR_CMD | 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits. |
| FDIN_DUAL | When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase. |
| FDOUT_DUAL | When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase. |
| FADDR_DUAL | When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase. |
| FDIN_QUAD | When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase. |
| FDOUT_QUAD | When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase. |
| FADDR_QUAD | When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase. |